1. Field of the Invention
The present invention relates to an analog/digital converting circuit which can accurately convert an analog input voltage to a digital value even if the analog input voltage exceeds a reference voltage.
2. Description of Related Art
An example of a conventional analog/digital converting circuit is disclosed in Japanese Patent Publication No. 60-57734 (1985). FIG. 1 is a block diagram showing the structure of the analog/digital converting circuit, in which conversion accuracy is, for example, 4 bits. Between a terminal supplied with a reference voltage V.sub.ref and a ground potential point is provided a series circuit including a resistor 11.sub.1 having a resistance of (3/2)R (wherein R is an appropriate resistance value), 14 resistors 11.sub.2 -11.sub.15 each having a resistance of R, and a resistor 11.sub.16 having a resistance of (1/2)R. Comparison voltages, i.e., voltages at connections a through o of these resistors are applied in parallel to an analog multiplexer 12. The analog multiplexer 12 appropriately selects and outputs the comparison voltages at three points among the connections a through o in accordance with a select code applied from a control circuit 14, which will be described later. At the start of analog/digital converting operation, it automatically selects the comparison voltages at the connections d, h and i.
The comparison voltages at the three points selected by the analog multiplexer 12 is supplied to a first input terminal of each of comparators 13.sub.1, 13.sub.2 and 13.sub.3. Each of the comparators 13.sub.1, 13.sub.2 and 13.sub.3 receives an analog input voltage AN.sub.in at a second input terminal in a parallel manner. Comparison output signals C.sub.1, C.sub.2 and C.sub.3 respectively supplied from the comparators 13.sub.1, 13.sub.2 and 13.sub.3 are applied to the control circuit 14 in a parallel manner. The control circuit 14 is provided with a control input terminal 15 which receives a conversion start signal ST for starting the analog/digital conversion, and the control circuit 14 applies a select code to the analog multiplexer 12 when it receives the conversion start signal ST.
Further, in response to the comparison output signals C.sub.1, C.sub.2 and C.sub.3 applied from the comparators 13.sub.1, 13.sub.2 and 13.sub.3 in the parallel manner, the control circuit 14 supplies a digital code corresponding to the comparison output signals C1, C.sub.2 and C.sub.3. The digital code is identical to the select code applied to the analog multiplexer 12. The digital code supplied from the control circuit 14 is inputted to a latch circuit 16 for temporarily storage, and thereafter is outputted via code terminals 17.sub.1 -17.sub.4. Further, the control circuit 14 is provided with a control output terminal 18 supplying a conversion end signal END indicating the end or termination of the analog/digital conversion.
Table 1 shows a relationship between each of the comparison voltages generated at the respective connections a-o of the resistors 11.sub.1 through 11.sub.16 and each of the digital codes 2.sup.-1, 2.sup.-2, 2.sup.-3 and 2.sup.-4.
TABLE 1 ______________________________________ Digital Code Connection Comparison Voltage 2.sup.-1 2.sup.-2 2.sup.-3 2.sup.-4 ______________________________________ 1 1 1 1 a 29/32 Vref 1 1 1 0 b 27/32 Vref 1 1 0 1 c 25/32 Vref 1 1 0 0 d 23/32 Vref 1 0 1 1 e 21/32 Vref 1 0 1 0 f 19/32 Vref 1 0 0 1 g 17/32 Vref 1 0 0 0 h 15/32 Vref 0 1 1 1 i 13/32 Vref 0 1 1 0 j 11/32 Vref 0 1 0 1 k 9/32 Vref 0 1 0 0 l 7/32 Vref 0 0 1 1 m 5/32 Vref 0 0 1 0 n 3/32 Vref 0 0 0 1 o 1/32 Vref 0 0 0 0 ______________________________________
The operation of the analog/digital converting circuit will now be described below with reference to Table 1.
When the analog/digital conversion is started by inputting the conversion start signal ST to the control input terminal 15 of the control circuit 14, the comparison voltages (23/32) V.sub.ref, (15/32)V.sub.ref and (7/32)V.sub.ref at the connections d, h and l, respectively are selected. Thus, the comparison voltages are selected at the connections d, h and l which quarters the voltage between the reference voltage V.sub.ref and the ground potential. The selected comparison voltages are supplied to comparators 13.sub.1, 13.sub.2 and 13.sub.3, respectively. At this point, the analog input voltage AN.sub.in to be converted into a digital value is supplied to the second input terminal of each of the comparators 13.sub.1, 13.sub.2 and 13.sub.3, so that the comparators 13.sub.1, 13.sub.2 and 13.sub.3 perform the first comparison between the supplied comparison voltages and the analog input voltage AN.sub.in.
When the analog input voltage AN.sub.in is larger than the comparison voltages selected by the analog multiplexer 12, the result of the first comparison is classified into the following four states (1), (2), (3) and (4) if the comparison output signals C.sub.1, C.sub.2 and C.sub.3 of the comparators 13.sub.1, 13.sub.2 and 13.sub.3 undergo a 0 to 1 transition.
State (1): C.sub.1 is at "1" level. PA1 State (2): C.sub.1 is at "0" level, and C.sub.2 is at "1" level. PA1 State (3): C.sub.1 and C.sub.2 are at "0" level, and C.sub.3 is at "1" level. PA1 State (4): C.sub.3 is at "0" level.
The result of the first comparison providing the state (1) is achieved when the analog input voltage AN.sub.in is larger than the comparison voltage (23/32)V.sub.ref at the connection d, and in this case, the control circuit 14 selects and outputs a digital code "1, 1, 1, 1," for performing the second comparison so as to select the connections a, b, and c quartering the voltage between the reference voltage V.sub.ref and the comparison voltage (23/32)V.sub.ref at the connection d. When this digital code is supplied to the analog multiplexer 12, the analog multiplexer 12 selects the comparison voltages (29/32)V.sub.ref, (27/32)V.sub.ref and (25/32)V.sub.ref at the connections a, b and c shown in Table 1. The selected comparison voltages are supplied to the comparators 13.sub.1, 13.sub.2 and 13.sub.3, respectively.
Thereafter, the second comparison is carried out to compare the comparison voltages supplied to the comparators 13.sub.1, 13.sub.2 and 13.sub.3 with the analog input voltage AN.sub.in. In this second comparison, if all the comparison output signals C.sub.1, C.sub.2 and C.sub.3 of the comparators 13.sub.1, 13.sub.2 and 13.sub.3 are at the level of "1", the control circuit 14 determines that the analog input voltage AN.sub.in is larger than the comparison voltage (29/32)V.sub.ref at the connection a, and continues to output the same digital code as that already outputted.
The latch circuit 16 temporarily stores the supplied digital code "1, 1, 1, 1", and then outputs it via the terminals 17.sub.1 -17.sub.4. As a result, the second comparison performs the analog/digital conversion of the analog input voltage AN.sub.in into the digital code "1, 1, 1, 1". Further, when the second comparison shows the result of comparison output signals C.sub.1 at "0" level and C.sub.2 and C.sub.3 at "1" level, the control circuit 14 determines that the analog input voltage AN.sub.in is smaller than the comparison voltage (29/32)V.sub.ref at the connection a and is larger than the comparison voltage (27/32)V.sub.ref at the connection b, and thus it changes only 2.sup.-3 and 2.sup.-4 of the digital code, which was previously outputted, into "1, 0" so as to select the connections b, c and d quartering the voltage between the comparison voltage (29/32)V.sub.ref at the connection a and the comparison voltage (23/32)V.sub.ref at the connection e, and outputs the same. Thus, the control circuit 14 outputs a digital code "1, 1, 1, 0".
When the second comparison provides the result of comparison output signal C.sub.1 and C.sub.2 at "0" level and C.sub.3 at "1" level, the control circuit 14 determines that the analog input voltage AN.sub.in is smaller than the comparison voltage (27/32)V.sub.ref at the connection b but is larger than the comparison voltage (25/32)V.sub.ref at the connection c, and thus it changes only 2.sup.-3 and 2.sup.-4 of the digital code, which was previously outputted, into "0, 1" so as to select the connections c, d and e quartering the voltage between the comparison voltage (27/32)V.sub.ref at the connection b and the comparison voltage (19/32) V.sub.ref at the connection f, and outputs the same. Thus, the control circuit 14 outputs a digital code "1, 1, 0, 1".
When the second comparison provides the result of comparison output signals C.sub.1, C.sub.2 and C.sub.3 at "0" level, the control circuit 14 determines that the analog input voltage AN.sub.in is smaller than the comparison voltage (25/32)V.sub.ref at the connection c but is larger than the comparison voltage (23/32)V.sub.ref at the connection d, and thus it changes only 2.sup.-3 and 2.sup.-4 of the digital code, which was previously outputted, into "0, 0" so as to select the connections d, e and f quartering the voltage between the comparison voltage (25/32)V.sub.ref at the connection c and the comparison voltage (17/32)V.sub.ref at the connection g, and outputs the same. Thus, the control circuit 14 outputs a digital code "1, 1, 0, 0".
After the second comparison, the latch circuit 16 temporarily stores the supplied digital code and thereafter outputs it via the code terminals 17.sub.1 -17.sub.4.
Meanwhile, when the result of the first comparison exhibits the state (2), i.e., C.sub.1 at "0" level and C.sub.2 at "1" level, the analog input voltage AN.sub.in is smaller than the comparison voltage (23/32)V.sub.ref at the connection d but is larger than the comparison voltage (15/32)V.sub.ref at the connection h. In this case, the control circuit 14 outputs a digital code "1, 0, 1, 1" for performing the second comparison so as to select the connections e, f and g quartering the voltage between the comparison voltage (23/32)V.sub.ref at the connection d and the comparison voltage (15/32)V.sub.ref at the connection h. When the digital code is supplied to the analog multiplexer 12, the analog multiplexer 12 selects the comparison voltages (21/32)V.sub.ref, (19/32)V.sub.ref and (17/32)V.sub.ref, respectively at the connections e, f and g.
The comparison voltages thus selected are supplied to the comparators 13.sub.1, 13.sub.2 and 13.sub.3, respectively. Thereafter, the comparators 13.sub.1, 13.sub.2 and 13.sub.3 perform the second comparison between the inputted comparison voltages and the analog input voltage AN.sub.in, similarly to the aforementioned case. In the second comparison, when at least the comparison output signal C.sub.1 among the comparison output signals C.sub.1, C.sub.2 and C.sub.3 of the comparators 13.sub.1, 13.sub.2 and 13.sub.3 is at the "1" level, the control circuit 14 determines that the analog input voltage AN.sub.in is larger than the comparison voltage (21/32)V.sub.ref at the connection e, and continues to output the digital code "1, 0, 1, 1", which was previously outputted, so as to select the connections f, g and h quartering the voltage between the comparison voltage (21/32)V.sub.ref at the connection e and the comparison voltage (13/32)V.sub.ref at the connection i.
When the second comparison exhibits the result of comparison output signals C.sub.1 at "0" level and C.sub.2 and C.sub.3 at "1" level, the control circuit 14 determines that the analog input voltage AN.sub.in is smaller than the comparison voltage (21/32)V.sub.ref at the connection e but is larger than the comparison voltage (19/32)V.sub.ref at the connection f, and thus it changes only 2.sup.-3 and 2.sup.-4 of the digital code, which was previously outputted, into "1, 0" so as to select the connections f, g and h quartering the voltage between the comparison voltage (21/32)V.sub.ref at the connection e and the comparison voltage (13/32)V.sub.ref at the connection i, and outputs the same. Thus, the control circuit 14 outputs a digital code "1, 0, 1, 0".
When the second comparison exhibits the result of comparison output signals C.sub.1 and C.sub.2 at "0" level and C.sub.3 at "1" level, the control circuit 14 determines that the analog input voltage AN.sub.in is smaller than the comparison voltage (19/32)V.sub.ref at the connection f but is larger than the comparison voltage (17/32)V.sub.ref at the connection g, and thus it changes only 2.sup.-3 and 2.sup.-4 of the digital code, which was previously outputted, into "0, 1" so as to select the connections g, h and i quartering the voltage between the comparison voltage (19/32)V.sub.ref at the connection f and the comparison voltage (11/32)V.sub.ref at the connection j, and outputs the same. Thus, the control circuit 14 outputs a digital code "1, 0, 0, 1".
If the second comparison exhibits the result of comparison output signals C.sub.1, C.sub.2 and C.sub.3 at "0" level, the control circuit 14 determines that the analog input voltage AN.sub.in is smaller than the comparison voltage (17/32)V.sub.ref at the connection g but is larger than the comparison voltage (15/32)V.sub.ref at the connection h, and thus it changes only 2.sup.-3 and 2.sup.-4 of the digital code, which was previously outputted, into "0, 0" so as to select the connections h, i and j quartering the voltage between the comparison voltage (17/32)V.sub.ref at the connection g and the comparison voltage (9/32)V.sub.ref at the connection k, and outputs the same. Thus, the control circuit 14 outputs a digital code "1, 0, 0, 0".
After the second comparison, the digital code inputted into the latch circuit 16 is temporarily stored, and then is outputted via the terminals 17.sub.1 -17.sub.4. Then, the operation will be performed similarly. More specifically, when the result of comparison after the first comparison exhibits the state (3) or (4), the control circuit 14 outputs a digital code "0, 1, 1, 1" or a digital code "0, 0, 1, 1", and thereafter the analog multiplexer 12 selects the respective comparison voltages at the connections i, j and k, or the respective comparison voltages at the connections m, n and o. In accordance with the comparison output signals C.sub.1, C.sub.2 and C.sub.3 of the comparators 13.sub.1, 13.sub.2 and 13.sub.3, the control circuit 14 outputs one of the digital code of 4 bits shown in Table 1. As a result, the latch circuit 16 outputs the digital code corresponding to the analog input voltage AN.sub.in.
When the latch circuit 16 completes the output of the 4-bit digital code via the code terminals 17.sub.1 -17.sub.4 after the second comparison, the control circuit 14 outputs the conversion end signal END via the control output terminal 18.
As described above, the conventional analog/digital converting circuit operates within a range from the ground potential to the reference voltage, and decompose the analog input voltage with accuracy of n bits (wherein n is a natural number) for converting an analog voltage into a digital value. This results in such a disadvantage that an analog input voltage cannot be accurately converted into a digital value, if the analog input voltage exceeds the reference voltage.